Clock and data recovery (CDR) circuits are extensively used in high speed serial data communications between integrated circuits/systems. The clock recovery (CR) circuit generates a recovered clock signal from the incoming data stream that is transmitted on a communication link which is subsequently used in the data recovery (DR) circuit for data capture using a single sampling pulse. In the case of long distance data communications, one CR circuit per communication link is required while in short-distance data communications, a single CR circuit is generally sufficient to interface with multiple communication links.
The performance of a CDR circuit is strongly tied to its jitter tolerance and to the incoming data stream jitter as well. However, the jitter tolerance is usually very low because the clock signal generator and CDR circuits are generally built using high stability Phase Locked Loop (PLL) oscillators, so that in turn, the recovered clock frequency is quite stable. On the other hand, in the case of a multiple channel serial data stream using a single CR circuit, there is an unpredictable phase difference (phase error) between data pertaining to different incoming data streams which limits the CR circuit jitter immunity. As a matter of fact, both phase error and jitter contribute to the reduction of the overall performance of multichannel CR circuits.
FIG. 1 shows the diagram of a typical 2.5 Gbits/s serial binary data (bits) stream signal consisting of one bit going from 0 to 1 and then back to 0 when the transmission is affected by a jitter (in this particular case, the frequency of the clock signal is half of the frequency of the incoming data). In FIG. 1, the bit boundaries are delimited by two transitions; when there is no change in the bit value, the bit boundaries are rather referred to as the bit edges. As apparent in FIG. 1, although the time-duration of a datum is about 400 ps, the useful window to perform a reliable sampling of the datum can be significantly shorter, e.g. 200 ps. Data jitter and/or phase error between the recovered clock and data signals can further reduce the useful sampling window. Moreover, circuit manufacturing process deviations, operating temperature and power supply variations can also have a negative impact on the targeted CDR circuit specifications. It is therefore difficult to ensure that the incoming data signal, which consists of a number of successive bits, is sampled in the centre of the bit time-duration.
FIG. 2 shows a typical multichannel data recovery (DR) circuit of the prior art referenced 10 placed in a receiver and adapted to interface with a transmitter in long distance serial data communications. Now turning to FIG. 2, DR circuit 10 is comprised of k blocks referenced 11-0 to 11-(k−1), one for each communication link, and a PLL (oscillator) 12 controlled by a reference clock (Ref. clock). The data that are serially transmitted are iso-synchronous on each of the k communication links. Each block 11 consists of a front end delay circuit 13 and a phase detector circuit 14 that are serially connected. Data-in 0 is applied to the delay circuit 13-0, in turn, the delayed data are applied to a first input of the phase detector circuit 14-0, the other input of which is connected to the output of PLL 12 which generates (at least) the two phase of a clock signal, one phase is used to detect the transition and the other to capture the data. The incoming data, e.g. data-in 0, is thus tuned by the front end delay circuit 13-0 while the phase detector circuit 14-0 controls the input delay to capture and reshape the data within each link to supply the recovered (or retimed) data-out 0 signal (the same principle applies to the other links). Circuit 10 has some inconveniences. First of all, delay elements 13 are noisy and then generate much jitter. In addition, because circuit 10 is synchronous, the PLL 12 needs to run at the same frequency for all the links, so that said transmitter and receiver need to be synchronized on the same reference clock signal because of the lack of a CR circuit. The reference clock needs to be transmitted in addition to the data, thus at the cost of an extra channel. As a result, circuit 10 is not adapted to long distance multiple channel serial data communications.
FIG. 3 shows a conventional clock and data recovery (CDR) circuit referenced 15. Now turning to FIG. 3, CDR circuit 15 consists of k identical blocks referenced 16-0 to 16-(k−1) one per communication link. The incoming data, e.g. data-in 0, is applied to the first input of phase and frequency detector (PFD) circuit 17-0 and to a first input of latch 18-0. The output of the PFD circuit 17-0 is connected to a PLL oscillator 19-0 via a filter 20-0 to stabilize the control signal which is applied thereon. PLL (oscillator) 19-0 generates two phases (at 90° shift) of a single clock signal, one is used to detect the transition in the incoming data and the other to capture the data as standard. A first output of PLL oscillator 19-0 is connected either directly or via a frequency divider to the other input of PFD circuit 17-0 and the second output thereof is connected to latch 18-0. Latch 18-0 generates the recovered (retimed) data-out 0 signal and the PLL 19-0 generates the recovered clock signal. The same construction applies to other communication links, so that trains of incoming data and related clock signals are recovered by the CDR circuit 15 in each channel. CDR circuit 15 is thus asynchronous which is a real advantage for long distance multichannel high speed serial communications. Unfortunately, this solution is relatively costly in terms of silicon area and power consumption. Unlike the DR circuit 10 implementation, the CDR circuit 15 requires a PLL, a filter and a PFD circuit for each link, that are known to occupy a large area on the silicon chip surface. In particular, the filter consumes a large area because it includes high value capacitors (sometimes packaged out of the silicon chip, for instance, mounted on the printed board itself). Moreover, because it is quite impossible to have a large number of PLL oscillators running at equivalent frequencies, the coupling between PLLs produces interference which are a big concern in terms of jitter. Finally, it is very unlikely, if not impossible, that the respective recovered clock signals are in phase. As a consequence, circuit 15 design is clearly not applicable to more than 4–8 channels.
Therefore, implementation of numerous channels (e.g. 16) that are now required for advanced long distance high speed multichannel serial data communications is not satisfactorily achieved to date.